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Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I 2 C-bus interface
8. Functional description
8.1 I 2 C-bus protocol
The I 2 C-bus is for 2-way, 2-line communication between different ICs or modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been de?ned:
? Data transfer may be initiated only when the bus is not busy.
? During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
9397 750 14219
8.1.1
8.1.2
Bus conditions
The following bus conditions have been de?ned:
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, de?nes the START condition.
Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, de?nes the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes, transferred between the START and STOP
conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within the I 2 C-bus speci?cations, a standard-speed mode (100 kHz clock rate) and a
fast-speed mode (400 kHz clock rate) are de?ned. The PCF8598C-2 operates in only
the standard-speed mode.
By de?nition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signal is called a ‘receiver’. The device which controls the signal is
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
put on the bus by the transmitter. The master generates an extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 22 October 2004
6 of 21
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